For the purpose of reducing the size and cost of liquid crystal display devices, development in technology has been made to integrate on a substrate, which is a liquid crystal display substrate, peripheral drive circuits such as data and gate driver circuits for driving data and gate lines of pixel matrices, respectively. A scanning circuit for generating gate scanning and sampling pulse signals is an essential circuit component among various circuits which constitute peripheral drive circuits.
The scanning circuit should be capable of bidirectionally scanning to meet the requirements for advanced functions such as display-reversing function of the liquid crystal display. In particular, in case where the liquid crystal display is used for a liquid crystal projector system, a function of reversing an image in vertical and/or horizontal directions depending upon the manner that an optical system and a projector are used in the projector system. Thus, the bidirectional scanning circuit is an essential circuit.
Such a type of bidirectional scanning circuit includes a circuit configuration as shown in FIG. 7, which is disclosed in, for example, Japanese Patent Kokai Publication JP-A-7-134277. Referring now to FIG. 7, the bidirectional scanning circuit comprises transfer gates 103-1 through 103-(N+1) of a transfer unit, which are in series connected with each other for transferring a signal from a previous stage to a next stage depending upon a rightward or leftward shift start pulse signal input from a first or second input terminal, respectively, in response to clocks A and B; feedback circuits 104-1 through 104N for preventing the magnitude (amplitude) of the transferred pulse signals from being attenuated; and output buffer circuits 105-1 through 105-N for outputting the outputs from the feedback circuits 104-1 through 104-N as OUT 1 through OUT N. The feedback circuits 104-1 through 104-N comprise inverters 106-1 through 106-N having input and output terminals which are connected to each other and clocked inverters 110-1 through 110-N as shown in FIG. 7. The clocked inverters 110-1 through 110-N are turned on or off in response to clock signals C and D.
The clocks A and B are alternatingly input to alternative gates of the n and p channel MOS transistors which form the transfer gates 103-1 through 103-(N+1) of the transfer unit. The clocks A and B are alternatingly input to the alternative clocked inverters 110-1 through 110-N of the feedback circuits 104-1 through 104-N.
FIG. 10 shows a circuit configuration of the clocked inverters 110-1 through 110-N. The symbol and circuit configuration of the clocked inverter circuit (transistors T3, T4) which supplies clock signals C and D to the gates of n and p channel transistors T2 and T1, respectively, is illustrated in FIG. 10(a). A symbol- and circuit-configuration of the clocked inverter circuit (transistors T3, T4) which supplies clock signals D and C to n and p channel MOS transistors T2 and T1, respectively, is illustrated in FIG. 10(b). The p and n channel MOS transistors T3 and T4 constitute a CMOS converter. Transistor T3, T4 are connected between a drain of the p channel MOS transistor T1 and a drain of the n channel MOS transistor T2, and have their gates which are commonly connected to each other and connected to an input terminal, with their drains being commonly connected to each other and connected to an output terminal. The CMOS inverter is turned on or off by turning on or off a current path between the power sources VDD and VSS depending upon the value of complimentary clocks C and D.
FIG. 8 is a timing chart explaining the operation of the prior art scanning circuit shown in FIG. 7. In the timing chart, wave forms of clocsk A to D and a signal on the terminal STR, signals OUT 1 to OUT N in case of rightward shift are illustrated.
In case of a rightward shift, a start pulse STR is input to a first input terminal STR in a timing relationship as shown in FIG. 8 and the second input terminal STL is opened. The clock signals A and D are a common clock φ and clock signals B and C are a common clock signal φ—(an inverted signal of the clock φ). The clocks A and B are complimentary two-phase signals and C and D are also complimentary two-phase signals.
A rightward shift scanning circuit is established by presetting clock signals A to D in such a manner, so that scanning pulse signals which are shifted in the order of from the scanning output OUT 1 to OUT N are output.
FIG. 9 is a timing chart in case of a leftward shift. In case of the leftward shift, a start pulse STL is input to a second input terminal STL in a timing relationship as shown in FIG. 9 and the first input terminal STR is opened. The clock signals A and C are a common clock φ and clock signals B and D are a common clock signal φ—(an inverted signal of the clock 4). The clock C and D are exchanged each other as compared to the case with the rightward shift.
A leftward shift scanning circuit is formed by presetting clock signals A to D in such a manner, so that scanning pulse signals which are shifted in the order of the scanning output OUT N to OUT 1 are output.
Use of the scanning circuit which is shown in FIG. 7 enables the shift direction to be switched without any additional circuit for switching the shift direction.